Hardware-based functional verification systems include logic emulation systems and simulation acceleration systems. In logic emulation systems, IC designs may be translated into an emulation image, and the emulation image run in the emulator. In simulation acceleration systems, IC designs may be divided into two parts, one part may be handled by a simulator, and another part may be handled by an emulator.
Compared to simulators, emulation systems have two major advantages. One advantage includes that the emulator may have dedicated hardware that performs the IC design functions in massive parallel, and therefore the emulator runs at a speed that is orders of magnitude faster than simulators. The other advantage is that the emulator can run with IC designs' real software systems and under IC designs' real target systems. In other words, emulator systems may emulate IC designs with a real system, so that IC designs' firmware and software systems may be tested with IC designs before IC designs are fabricated.
Verification of a low power design in the early design stage is becoming more popular and in demand. A low power design includes an IC design with low power intent. In general, the IC design's functional part may be written in an HDL (Hardware Design Language), such as Verilog/System Verilog, and Very High Speed Integrated Circuit HDL (VHDL). The IC design's power intent may be specified in low power intent languages, such as Institute of Electrical and Electronics Engineers (IEEE) 1801 UPF (Unified Power Format) or CPF (Common Power Format). Power intent files can be either a UPF or a CPF file.
A coverage metrics report may be a good measurement of the completeness of IC designs' verification. System Verilog includes a coverage mechanism for code coverage and function coverage. This guides the IC designs' HDL coverage metrics and report. Users may generate reports on code coverage and function coverage for low power objects based on UPF or CPF files' contents.
Simulators may include low power coverage. Current simulator technologies can create System Verilog files that include coverage models and/or coverage groups within their design. This approach may require re-compilation and complicate the compilation process. This approach also may require the installation of coverage monitors, which impacts simulation performance. There is a need, therefore, for a different approach for emulator low power coverage, with less performance impact.